june 21 , 201 3 | final | v1. 0 9 1 digital multi - p hase buck controller ir3541a a/b features ? 5 - phase dual output pwm controller ? phases are flexibly assigned between loops 1 & 2 ? intel? vr12, amd? 400khz & 3.4mhz svi and memory modes ? dual ocp support for i - spike enhanced amd cpus ? smb_alert pin for servers ? pmbus address pin or variable gate drive ? overclocking & gaming mode with vmax setting ? switching frequency from 200khz to 1.2mhz per phase ? ir efficiency shaping features including variable gate drive and dynamic phase control ? programmable 1 - phase or 2 - phase for light loads and active diode emulation for very light loads ? ir adaptive transient algorithm (ata) on both loops minimizes output bulk capacitors and system cost ? auto - phase detection with auto - compensation ? per - loop fault protection: ovp, uvp, ocp, otp, cfp ? i2c/smbus/pmbus system int erface for telemetry of temperature, voltage, current & power for both loops ? non - volatile memory (nvm) for custom configuration ? compatible with ir atl and 3.3v t ri - state drivers ? +3.3v supply voltage; - 20oc to 85oc ambient operation ? pb - free, rohs, 6 x 6 4 0 - pin qfn , msl2 package applications ? intel ? vr12 & amd? svi based systems ? ddr memory with vtt tracking ? overclocked & gaming platforms description the ir3541a is a dual - loop , digi tal multi - phase buck controller that drive up to 5 phases. the ir3541a is fully intel? vr12 and amd? svi compliant on both loops and provides a vtt tracking function for ddr memory. nvm storage saves pins and enables a small package size. the ir3541a include s the ir efficiency shaping technology to deliver exceptional efficiency at minimum cost across the entire load range. ir variable gate drive optimizes the mosfet gate drive voltage as a function of real - time load current. ir dynamic phase control adds/drops active phases based upon load current. the ir3541a can be configured to e nter 1 - phase operation and active diode emulation mode automatically or by command . irs unique adaptive transient algorithm (ata), based on proprietary non - linear digital pwm algorithms, minimizes output bulk capacitors. the i2c/pmbus interface can commu nicate with up to 16 ir3541a based vr loops. device configuration and fault parameters are easily defined using the ir intuitive power designer ( dpdc ) gui and stored in on - chip nvm. the ir3541a also include s numerous features like register diagnostics for fast design cycles and platform differentiation, truly simplifying vrd design and enabling fastest time - to - market with its set - and - forget methodology . pin diagram figure 1 : ir3541a package top view ir3541a
june 21 , 201 3 | final | v1. 0 9 2 digital multi - p hase buck controller ir3541a a/b ordering information ir35 41 a m ? ? ? ? ? ? ? ? ? package packing qty part number programming qfn tr= 3000 ty=4900 ir35 41 amtrpbf ir35 41 amt y pbf default qfn tr= 3000 ir35 41 amxxyytrp 1 customer configuration notes: 1. xx = customer id and yy = configuration file ( codes assigned by ir marketing). figure 2 : ir35 41 a package top view, enlarged p/pbf C lead free tr C tape & reel / ty - tray yy C configuration file id xx C customer id package type (qfn) ir3541a
june 21 , 201 3 | final | v1. 0 9 3 digital multi - p hase buck controller ir3541a a/b fu nctional block diagr am figure 4 : ir3541a functional block diagram i s e n 1 i r t n 1 i s e n 2 i r t n 2 i s e n 3 i r t n 3 i s e n 4 i r t n 4 i s e n 5 i r t n 5 t s e n v i n s e n v o l t a g e a d c v s e n v r t n c o n t r o l a n d m o n i t o r i n g p w m g e n e r a t o r v o u t 1 _ e r r o r v o u t 2 _ e r r o r p w m 1 p w m 2 p w m 3 p w m 4 p w m 5 r e f e r e n c e , o s c i l l a t o r , s t a t e c o n t r o l , i n t e r f a c e s , r e g i s t e r s a n d n v m s m b _ d i o a d c c l o c k s m u x c l o c k s p h a s e _ p e r i o d _ 1 p h a s e _ p e r i o d _ 2 v 3 _ 3 i o u t v i n t e m p f a u l t b u s s y s t e m c l o c k i o u t v i n t e m p v o u t f a u l t b u s s y s t e m c l o c k v i d _ 1 v i d _ 2 c u r r e n t a d c i t o t _ 1 i t o t _ 2 i p 1 i p 2 i p 3 i p 4 i p 1 i p 2 i p 3 i p 4 i p 5 m o d e c o n t r o l i p 5 v a r _ g a t e _ p m _ a d d r ( c h l 8 3 2 5 a ) l d o v c c 1 . 8 v v 1 8 a s m b _ c l k s m b _ a l e r t # e n v r _ h o t # 1 / v r h o t _ i c r i t # 2 v r _ r e a d y _ l 1 1 / p w r g d 2 v r _ r e a d y _ l 2 1 / p w r o k 2 p h a s e _ p e r i o d _ 1 p h a s e _ p e r i o d _ 2 r r e s r c s p r s c m a f e _ 1 v i d _ 1 s v _ a l e r t # 1 / v f i x e n 2 s v _ c l k 1 / s v c 2 s v _ d i o 1 / s v d 2 n o t e s 1 p i n d e f i n i t i o n i n i n t e l & m p o l m o d e s 2 p i n d e f i n i t i o n i n a m d m o d e t s e n 2 ( c h l 8 3 2 5 b ) v s e n _ l 2 v r t n _ l 2 r c s p _ l 2 r s c m _ l 2 a f e _ 2 i t o t _ 2 v i d _ 2 m o n i t o r a d c
|
